The present invention relates to semiconductor memory devices, and more particularly to a word line driving circuit for driving a word line by decoding a row address.
Typically, each memory cell of a dynamic random access memory (DRAM) includes one access transistor and one storage capacitor and data is stored in the storage capacitor. The data stored in the storage capacitor is transferred to a bit line through the channel of the access transistor. When the data is transferred to the bit line, the transfer speed and the voltage level of the bit line are determined by the voltage level of the word line applied to the gate of the access transistor. However, in the case of a highly integrated semiconductor memory device using a low supply voltage, since the voltage level of the word line applied to the gate of the access transistor is not great enough to transfer the data stored in the storage capacitor to the bit line, there are disadvantages such as the reduction of the operating speed of the memory device.
FIG. 1 illustrates a conventional word line driving circuit of a semiconductor memory device having a bootstrap circuit, and FIG. 2 a timing chart showing the operation of the circuit of FIG. 1. The circuit structure of FIG. 1 is well known in the art as a row decoder. Hereinafter it is referred to as a word line driving circuit. Referring to FIG. 1, a boosting signal .0.X is transferred to a word line WL through an NMOS transistor 9 having its source electrode connected thereto. The boosting signal .0.X is generated from a peripheral circuit located outside of a memory array block and is driven to a voltage level of Vcc+2Vt (Vt is a threshold voltage of a transistor) during an active cycle of a chip. If the boosting signal .0.X is transferred to the word line, the data stored in the storage capacitor is transferred to the bit line through the channel of the access transistor of the memory cell. Decoded row address signals DRAij, DRAkl and DRAmn are related to block selection. Referring to FIG. 2, a signal .0.ORD is a delayed signal of a row strobe signal/RAS and directly enables each operating signal of FIG. 1. If the row address strobe signal/RAS is an active state, a signal PDPX is set to logic "high" level and a precharge transistor 1 is turned off. Then a row address passing through a predecoder (not shown and positioned at each input portion of a row decoder or a column decoder) is applied. If all the decoded row address signals DRAij, DRAkl and DRAmn are logic "high" level, a node n1 is set to logic "low" level. Then a node n2 for controlling the word line WL is precharged to a level of Vcc-Vt8 (Vt8 is the threshold voltage of an NMOS transistor 8). Thereafter if the boosting signal .0.X is applied, the node n2 is self-boosted through the NMOS transistor 9 and the boosting signal .0.X is transferred to the word line WL through the NMOS transistor 9.
In the circuit of FIG. 1, the node n2 should be precharged to a level of Vcc-Vt8 before the boosting signal .0.X is applied. However, at a low supply voltage, since the precharge level of the node n2 is not sufficient, the operating characteristic deteriorates and the voltage boosting level of the word line WL is reduced. In addition, since the boosting signal .0.X should be applied after the node n2 is sufficiently precharged, the operating speed is reduced. In this case, since the node n2 is set to a level of Vcc-Vt8 +.0.X instead of a constant voltage level, the reliability of the word line driving circuit is lowered. In the meanwhile, if the voltage level of the word line WL is raised, the gate-source voltage Vgs of the NMOS transistor 9 is reduced, and thus, a charge sharing operation between the word line WL and the boosting signal .0.X through the channel of the NMOS transistor 9 is insufficiently performed at a falling part of the voltage level of the boosting signal .0.X.
Another example of a conventional word line driving circuit which overcomes the aforementioned problems is shown in FIG. 3. The circuit of FIG. 3 is described in a paper by K. Komatsuzaki et al. entitled, "Circuit Techniques for a Wide Word I/O Path 64 Mega DRAM", 1991 SYMPOSIUM ON VLSI CIRCUITS. To solve the problems of the circuit of FIG. 1, the word line boosting signal .0.X is transferred to the word line through a PMOS transistor 30 which is a word line driver. That is, the device characteristics of the PMOS transistor are used. In FIG. 3, a latch circuit 40 is driven from decoded row address signals and the word line driver 30 is driven by the latch circuit 40. If the latch circuit 40 generates a pumping voltage Vpp (higher than a supply voltage Vcc and generated from, for example, a pumping circuit within the chip), the voltage of the word line WL is set to logic "low" level through an NMOS transistor 31. If the latch circuit 40 generates logic "low" level, the PMOS transistor 30 of the word line driver is turned on and the word line boosting signal .0.X of the word line driver is directly transferred to the word line WL. Since the word line driver is the PMOS transistor 30, the output signal of the latch circuit 40 is not boosted. Therefore, the word line boosting signal .0.X is transferred to the word line WL without boosting the gate voltage of the word line driver. The circuit of FIG. 3 ameliorates the aforementioned disadvantages, such as the deterioration of the operating characteristic and the reduction of the voltage boosting level of the word line WL caused by the insufficient precharge level of the gate voltage of the word line driver at the low supply voltage, and the reduction of the operating speed generated when the word line boosting signal .0.X is applied after sufficiently precharging the gate voltage of the word line driver.
However, there are still drawbacks. That is, since the decoded row address signals RA0, . . . RA3 and a precharge control signal/PC perform a swing operation from a ground voltage Vss to a supply voltage Vcc and the operating voltages of input terminals 19, 20, . . . 25 are the supply voltage Vcc, the latch circuit 40 is necessarily needed. To design the word line driving circuit as shown in FIG. 3 in the memory cell array to which the design rule of submicron order is applied in proportion to the number of memory cells is very difficult and inefficient. Since the precharge control signal/PC and decoded row address signals RAO, . . . , RA3 are applied to the input terminals 19, 20, . . . , 25 and the decoded row address signals RAO, . . . RA3 of logic "low" level are applied after the precharge control signal/PC is fully set to logic "high" level, a delay phenomenon occurs due to the enable sequence of signals. Further, there is signal line loading of the precharge control signal/PC caused by applying the precharge control signal/PC to the multiple word line driving circuits which exist in the chip, and thus the channel size of the output terminal of a precharge control signal generating circuit should be enlarged. Hence, the output signal is delayed.